Input and output buffers are commonly used in a wide variety of electrical devices to couple digital signals to or from the electrical devices. The buffers generally provide a high input impedance to avoid excessively loading circuits to which they are connected, and they have a low output impedance to simultaneously drive electrical circuits without excessive loading. Input buffers are used, for example, to couple command, address and write data signals from command, address and data buses, respectively, of memory devices, including dynamic random access memory (“DRAM”) devices. Output buffers are used in memory devices, for example, to couple read data to the data bus.
As the operating speed of memory devices continues to increase, the timing at which command, address and write data signals, as well as other signals, are coupled to circuits in memory devices has become more critical. Similarly, the timing at which read data signals are coupled to external devices, such as memory controllers, has also become more critical. The manner in which input buffers and output buffers couple signals has therefore become very important to the high speed operation of memory devices. With reference to FIG. 1A, an input signal SIN applied to a buffer transitions from a low or binary “0” value to a high or binary “1” value at time t0. The input signal SIN then transitions from the high value to the low value at time t2. In many cases, the voltage of the input signal SIN is compared to a reference voltage VREF, and the buffer switches when the magnitude of the input signal SIN increases above VREF or decreases below VREF.
In response to the transitions of the input signal SIN, the buffer produces an output signal SOUT, which is shown in FIG. 1B. In response to the low-to-high transition of the input signal SIN, the output signal SOUT also transitions from low-to-high, and it reaches the midpoint of such transition at time t1. Similarly, the SOUT signal reaches the midpoint of its high-to-low transition responsive to the high-to-low transition of the input signal at time t3. The delay of the output signal SOUT after the low-to-high transition of the SIN signal is commonly designated as tPLH. Similarly, the delay of the output signal SOUT after the high-to-low transition of the SIN signal is commonly designated as tPHL. It is desirable for the magnitude of tPLH to be the same as the magnitude of tPHL, which requires that the buffer have symmetrical operating characteristics. It is generally even more important that tPLH and tPHL remain constant despite environmental changes, such as changes in the magnitude of a supply voltage VCC or the reference voltage VREF. Otherwise, timing relationships will vary with these environmental changes, thus making it impossible for memory devices to operate at very high speeds where timing tolerances are very small.
FIGS. 1A and 1B show the operation of a “single-ended” buffer that receives a single input signal SIN and outputs a single output signals SOUT. However, buffers used in memory devices and other electronic devices are often differential buffers that receive complementary input signals SIN, SIN* and output complementary output signals SOUT, SOUT*. However, variations are also common, such as buffers that receive a single input signal SIN and output complementary output signals SOUT, SOUT* as well as buffers that receive complementary input signals SIN, SIN* and output a single output signals SOUT.
The operating characteristics of a buffer receiving complementary input signals SIN, SIN* and outputting complementary output signals SOUT, SOUT* is shown in FIGS. 2A and 2B. With reference to FIG. 2A, complementary input signals SIN, SIN* applied to a buffer have a first transition at time t0 and a second transition opposite the first transition at time t2. The voltage of the input signals SIN, SIN* are generally compared to each other, and the buffer switches when the magnitude of the input signal SIN increases above the SIN* signal or decreases below the SIN* signal.
As shown in FIG. 2B, the output signals SOUT, SOUT* transition in response to the first and second transitions of the input signals SIN, SIN* at times t1 and t2, respectively. Again, the delay between t0 and t1 can be designated as tPLH, and the delay between t2 and t3 can be designated as tPHL. It is also important for tPLH to have the same as the magnitude as tPHL, and for both of those parameters to be insensitive to environmental changes.
A variety of input buffers and output buffers are in common use. Some of these buffers have non-symmetrical topologies that tend to result in non-symmetrical operating characteristics. Even if the buffers do not have non-symmetrical operating characteristics, their tPLH and tPHL parameters may vary excessively with environmental changes. For example, a self-biased differential amplifier 10 as shown in FIG. 3 is commonly used as an input buffer in memory devices. The amplifier 10 includes a pair of PMOS transistors 14, 16 coupled to each other and to a supply voltage VCC to act as a current mirror so that current through the transistor 14 is equal to the current through the transistor 16. The current mirror operates by the transistor 14 sensing the current passing through it and generating a voltage that is used to control both transistors 14, 16. The drains of the transistors 14, 16 are coupled to respective NMOS transistors 20, 24, which receive complementary input signals VIN+ and VIN− at their gates, respectively. However, a reference voltage is often applied to the amplifier 10, and the amplifier operates as a “single-ended” amplifier receiving a single input signal. The transistors 20, 24 function as a differential amplifier to produce an output signal VOUT+ at the drain of the NMOS transistor 24 that has a magnitude that is proportional to the difference between VIN+ and VIN−. However, in other implementations, the amplifier 10 produce output signal VOUT+ and VOUT− at the drain of the NMOS transistor 24 and the drain of the NMOS transistor 20, respectively. Finally, an NMOS transistor 28 coupled to the sources of both NMOS transistors 20, 24 acts as a current sink to set the current flowing through the transistors 20, 24. The transistor 28 is biased by coupling its gate to the drain of the transistor 20.
The differential amplifier is referred to as “self-biased” because the bias voltage applied to the gate of the current sink transistor 28 is automatically adjusted to maintain the current through the transistor 28 constant as the supply voltage VCC and the temperature of the amplifier 10 change. For example, if the current is reduced because of these changes, the voltage drop across the PMOS transistor 14 is reduced so that the bias voltage applied to the gate of the current sink transistor 28 is increased. As a result, the current through the PMOS transistor 14 is brought back to its original value. In a similar manner, if the current through the transistor 14 increases, the bias voltage applied to the gate of the current sink transistor 28 decreases so that the transistor 28 reduces the current through the PMOS transistor 14 back to its original value.
The self-biased differential amplifier 10 provides good performance in a large number of applications. It is partly for that reason it is so widely used. However, it is apparent from FIG. 3 that the amplifier 10 has a non-symmetrical topology. In particular, the drain of only the PMOS transistor 14 is connected to the gates of the transistors 14, 16. The gate of the PMOS transistor 16 has no similar connection. Furthermore, the output signal VOUT+ of the differential amplifier 10 is taken from the drain of the NMOS transistor 24. Even if the amplifier 10 provided a differential output by taking an output signal from the drain of the NMOS transistor 20, the amplifier would still have a non-symmetrical topology.
The non-symmetrical topology of the amplifier 10 causes its operating characteristics to be non-symmetrical so that response of the amplifier 10 to low-to-high transitions of the input signals VIN+ and VIN−, i.e., tPLH, does not match the response of the amplifier 10 to high-to-low transitions of the input signals VIN+ and VIN−, i.e., tPHL. Similar problems exist for other input and output buffer circuits that have non-symmetrical topologies.
There is therefore a need for a buffer circuit that has a symmetrical configuration so that it responds to low-to-high transitions of input signals in the same manner that it responds to high-to-low transitions of input signals.